Optimization of delay in global interconnect paths has long been a goal in the design of integrated circuits. A number of algorithms and design techniques have been used to optimize delay and timing slack in designs utilizing submicron device fabrication technologies. With the continued scaling of process technology, however, unwanted capacitive coupling of signals between adjacent interconnect wires on an integrated circuit becomes a very real problem. This phenomenon is referred to as crosstalk. The occurrence of crosstalk on certain operations can cause a chip to malfunction, for example, when a noise glitch is induced on a metal line as a consequence of a fast switching operation on a nearby line.
FIG. 1 shows an analog model for internally induced crosstalk noise during operation of a logic network. Gate 10 drives net 14 that includes a metal interconnect line with resistance modeled as R1–R3. Capacitors C1–C4 represent the capacitive coupling between net 14 and neighboring net 15, which includes gates 11 & 12 and associated physical parameters modeled by resistors R4-R8 and capacitors C5–C8. (It is appreciated that inductive coupling may also be present, although not specifically shown in the figure.) In the context of this discussion, net 14 causes the unwanted interference with net 15 by producing an unwanted noise glitch at the input of gate 12 when the output of gate 10 switches rapidly. In such a model, net 14 is referred to as the aggressor, and net 15, which suffers unwanted interference from the crosstalk-induced glitch, is called the victim. A functional malfunction can occur when the magnitude of the crosstalk-induced glitch is larger than the noise margin at the input node of gate 12 and the resulting glitch propagates to a storage element. When this happens, the logic state of the victim net can flip (e.g., from a logical “1” to a logical “0”, or vice-versa).
One common solution to the problem of network malfunctions caused by glitch noise has been insertion of one or more buffers in the victim net. These buffers are typically selected from a standard cell library and function to distribute the capacitive coupling between the newly created wires. The problem with this approach, however, is that significant additional signal delay can be introduced. Furthermore, often times there is no available space in the existing circuit layout for a set of buffer cells to be added. Moreover, because standard cell buffers are usually optimized for propagation delay, the slew rate tends to be sharper on the newly created wire segments where the buffers have been inserted. This can create new noise problems, i.e., where the victim net becomes the aggressor.
What is needed, therefore is a new solution to the existing problem of crosstalk in the design of high performance integrated circuits.